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BCS-111 • Block 1 Unit 1✍️ Author: Er. Manoj Kumar

Unit 1: Introduction to Computer Systems & Data Representation 💻

Explore the core building blocks of a computer, Von Neumann architecture, binary/hexadecimal data representation, and fundamental logic gates with visual diagrams.

Mode: ENGLISH (EASY Level)
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1. Functional Building Blocks of a Computer 🏗️

Every computer system is composed of three primary functional subsystems working in synchronization:

1
Central Processing Unit (CPU):

• Control Unit (CU): Directs the flow of data and decodes program instructions.

• Arithmetic Logic Unit (ALU): Performs arithmetic computations (+, -, *, /) and logical evaluations (AND, OR, NOT).

• Registers: High-speed internal memory cells (e.g. Program Counter PC, Accumulator ACC, Instruction Register IR).

2
Main Memory Unit (RAM/ROM):

Holds active program instructions and transient data required immediately by the CPU.

3
Input/Output (I/O) Peripherals:

Enables user interaction (Keyboards, Mice, Displays, Mass Disk Storage).

C++ Architecture Code Sample
// Basic C++ Simulation of CPU Input-Process-Output (IPO) Cycle
#include <iostream>

int main() {
    int inputData = 42; // Input stage
    int result = inputData * 2; // Process stage (ALU)
    std::cout << "CPU Output: " << result << std::endl; // Output stage
    return 0;
}
Developer Key Takeaways
  • CPU is the central brain containing CU, ALU, and Registers.
  • Program Counter (PC) stores the memory address of the next instruction to execute.
  • Accumulator (ACC) temporarily stores intermediate ALU calculation results.

2. The Stored Program Concept & Von Neumann Architecture 🧠

Proposed by John von Neumann, the Stored Program Concept dictates that both program instructions and data reside together in the same unified primary memory.

Von Neumann Bottleneck:

Because data and instructions share the single system bus connecting CPU to RAM, instructions cannot be fetched at the exact same instant that data is read or written. This sequential throughput limit is called the Von Neumann Bottleneck.

Harvard Architecture Alternative:

Unlike Von Neumann, Harvard Architecture utilizes separate physical buses and memory units for instructions and data, allowing simultaneous instruction fetch and data access.

Developer Key Takeaways
  • Von Neumann Architecture uses a single shared bus for data and instructions.
  • Harvard Architecture uses separate dedicated buses for faster parallel access.

3. Data Representation & Number System Conversions 🔢

Computers use binary states (0s and 1s) representing low and high voltages.

Number Systems:

• Decimal (Base-10): Digits 0-9

• Binary (Base-2): Digits 0, 1

• Octal (Base-8): Digits 0-7

• Hexadecimal (Base-16): Digits 0-9 and Letters A-F (where A=10, F=15)

Conversion Example (Decimal 25 to Binary):

25 / 2 = 12 (Remainder 1)

12 / 2 = 6 (Remainder 0)

6 / 2 = 3 (Remainder 0)

3 / 2 = 1 (Remainder 1)

1 / 2 = 0 (Remainder 1)

Reading remainders bottom-to-top gives: 11001₂.

Developer Key Takeaways
  • 1 Byte = 8 Bits. 1 Nibble = 4 Bits.
  • Hexadecimal simplifies long binary strings (e.g. 1111₂ = F₁₆).

4. Fundamental Logic Gates ⚡

Logic gates are hardware building blocks that process binary inputs to produce a single binary output:

• AND Gate: Output is 1 ONLY if ALL inputs are 1.

• OR Gate: Output is 1 if AT LEAST ONE input is 1.

• NOT Gate (Inverter): Inverts input (0 ➔ 1, 1 ➔ 0).

• NAND Gate: Universal gate (Opposite of AND).

• NOR Gate: Universal gate (Opposite of OR).

• XOR Gate: Output is 1 if inputs are DIFFERENT.

Developer Key Takeaways
  • NAND and NOR are Universal Gates because any logic circuit can be built using only NAND or NOR gates.
  • XOR is used in binary adders for arithmetic operations.

Interactive Computer Architecture Tool: Base Converter

Type any integer below to see how the CPU represents it across Binary, Octal, and Hexadecimal registers.

Binary (Base 2)
101010
Octal (Base 8)
52
Hexadecimal (Base 16)
0x2A

Unit Mastery Quiz

Test your understanding in ENGLISH.

Q1. Which CPU register stores the memory address of the NEXT instruction to be fetched and executed?
Q2. Fill in the blank: The speed bottleneck caused by sharing a single bus for both data and instructions is called the ______ Bottleneck.
Select Option Pill:
Official IGNOU & Developer Reference Links
eGyanKosh Official IGNOU PortalIGNOU BCA 1st Semester Hub